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PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 notice: the information in this document is subject to change without notice. pulsecore semiconductor corporation 1715 s. bascom ave suite 200 campbell, ca 95008 ? tel: 408-879-9077 ? fax: 408-879-9018 www. p ulsecoresemi.com low frequency timing-safe? peak emi reduction ic general features ? low frequency clock distribution with timing- safe? peak emi reduction ? input frequency range: 4mhz - 20mhz ? multiple low skew timing-safe? outputs: pcs3p622z05: 5 outputs pcs3p622z09: 9 outputs ? external input-output delay control option ? supply voltage: 3.3v0.3v ? commercial and industrial temperature range ? packaging information: asm3p622z05: 8 pin soic, and tssop asm3p622z09:16 pin soic, and tssop ? true drop-in solution for zero delay buffer, asm5p2305a / 09a functional description pcs3p622z05/09 is a versatile, 3.3v zero-delay buffer designed to distribute low frequency timing-safe? clocks with peak emi reduction. pcs3p622z05 is an eight-pin version, accepts one reference input and drives out five low-skew timing-safe? clo cks. pcs3p622z09 accepts one reference input and drives out nine low-skew timing- safe?clocks. pcs3p622z05/09 has a dly_ctrl for adjusting the input-output clock delay, de pending upon the value of capacitor connected at this pin to gnd. pcs3p622z05/09 operates from a 3.3v supply and is available in two different packages, as shown in the ordering information table, over commercial and industrial temperature range. application pcs3p622z05/09 is targeted for use in displays and memory interface systems. general block diagram pll dly_ctrl clkout1 clkout2 clkout3 clkout4 PCS3P622Z05B/c clkin pcs3p622z09b/c clkin dly_ctrl pll mux clkouta1 clkouta2 clkouta3 clkouta4 clkoutb1 clkoutb2 clkoutb3 clkoutb4 select input decoding s2 s1
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 2 of 15 notice: the information in this document is subject to change without notice. spread spectrum frequency generation the clocks in digital systems are typically square waves with a 50% duty cycle and as frequencies increase the edge rates also get faster. analysis shows that a square wave is composed of fundamental frequency and harmonics. the fundamental frequency and harmonics generate the energy peaks that become the source of emi. regulatory agencies test electronic equipment by measuring the amount of peak energy radiated from the equipment. in fact, the peak level allowed decreases as the frequency increases. the standard methods of reducing emi are to use shielding, filtering, multi-layer pcbs etc. these methods are expensive. spread spectrum clocking reduces the peak energy by reducing the q factor of the clock. this is done by slowly modulating the clock frequency. the pcs3p622z05/09 uses the center modulation sp read spectrum technique in which the modulated output frequency varies above and below the reference frequency with a specified modulation rate. with cent er modulation, the average frequency is the same as the unmodulated frequency and there is no performance degradation zero delay and skew control all outputs should be uniformly loaded to achieve zero delay between input and output. since the dly_ctrl pin is the internal feedback to the pll, its relative loading can adjust the input-output delay. for applications requiring ze ro input-output delay, all outputs, including dly_ctrl, must be equally loaded. even if dly_ctrl is not used , it must have a capacitive load equal to that on other outputs, for obtaining zero- input-output delay. timing-safe? technology timing-safe? technology is the ability to modulate a clock source with spread spectrum technology and maintain synchronization with any associated data path.
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 3 of 15 notice: the information in this document is subject to change without notice. pin configuration for PCS3P622Z05B/c pin description for PCS3P622Z05B/c pin # pin name type description 1 clkin 1 i external reference clock input, 5v tolerant input 2 clkout1 2 o buffered clock output 4 3 clkout2 2 o buffered clock output 4 4 gnd p ground 5 clkout3 2 o buffered clock output 4 6 vdd p 3.3v supply 7 clkout4 2 o buffered clock output 4 8 dly_ctrl o external input-output delay control . this pin can be used as clock output 4 clkin clkout1 1 2 3 4 5 6 7 8 PCS3P622Z05B/c gnd clkout3 vdd dly_ctrl clkout2 clkout4
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 4 of 15 notice: the information in this document is subject to change without notice. pin configuration for pcs3p622z09b/c pin description for pcs3p622z09b/c pin # pin name pin type description 1 clkin 1 i external reference clo ck input, 5v tolerant input 2 clkouta1 2 o buffered clock bank a output 4 3 clkouta2 2 o buffered clock bank a output 4 4 vdd p 3.3v supply 5 gnd p ground 6 clkoutb1 2 o buffered clock bank b output 4 7 clkoutb2 2 o buffered clock bank b output 4 8 s2 3 i select input, bit 2.see select input decoding table for pcs3p622z09 for more details 9 s1 3 i select input, bit 1.see select input decoding table for pcs3p622z09 for more details 10 clkoutb3 2 o buffered clock bank b output 4 11 clkoutb4 2 o buffered clock bank b output 4 12 gnd p ground 13 vdd p 3.3v supply 14 clkouta3 2 o buffered clock bank a output 4 15 clkouta4 2 o buffered clock bank a output 4 16 dly_ctrl 2 o external input-output delay control . this pin can be used as clock output notes: 1. weak pull down 2. weak pull-down on all outputs 3. weak pull-up on these inputs 4. buffered clock output is timing-safe? 1 2 3 4 13 14 15 16 pcs3p622z09b/c 5 6 7 8 9 10 11 12 clkouta3 clkouta4 clkoutb3 clkoutb4 vdd gnd s1 dly _ ctrl vdd gnd clkoutb1 clkoutb2 clkouta1 clkin clkouta2 s2
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 5 of 15 notice: the information in this document is subject to change without notice. select input decoding table for pcs3p622z09 s2 s1 clkout a1 - a4 clkout b1 - b4 dly_ctrl 1 output source pll shut-down 0 0 three-state thr ee-state driven pll n 0 1 driven three-st ate driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n notes: this output is driven and has an internal feedback for t he pll. the load on this output can be adjusted to change the sk ew between the reference and the output. spread spectrum control and input-output skew table frequency (mhz) device deviation ( %) input-output skew (t skew ) PCS3P622Z05B / 09b 0.25 0.0625 12 pcs3p622z05c / 09c 0.5 0.125 note: t skew is measured in units of the clock period absolute maximum ratings symbol parameter rating unit vdd supply voltage to ground potential -0.5 to +4.6 vin dc input voltage (clkin) -0.5 to +7 v t stg storage temperature -65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22- a114-b) 2 kv note: these are stress ratings only and are not implied for functional use. exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. operating conditions parameter description min max unit vdd supply voltage 3.0 3.6 v t a operating temperature (ambie nt temperature) -40 +85 c c l load capacitance 30 pf c in input capacitance 7 pf
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 6 of 15 notice: the information in this document is subject to change without notice. electrical characteristics parameter description test conditions min typ max unit v il input low voltage 5 0.8 v v ih input high voltage 5 2.0 v i il input low current v in = 0v 50 a i ih input high current v in = vdd 100 a v ol output low voltage 6 i ol = 8ma 0.4 v v oh output high voltage 6 i oh = -8ma 2.4 v i dd supply current unloaded outputs 18 ma z o output impedance 23 ? note: 5. clkin input has a threshold voltage of vdd/2 6. parameter is guaranteed by design and characterization. not 100% tested in production switching characteristics parameter test conditions min typ max unit input frequency 4 20 mhz output frequency 30pf load 4 20 mhz duty cycle 7,8 = (t 2 / t 1 ) * 100 measured at vdd/2 40 50 60 % output rise time 7, 8 measured between 0.8v and 2.0v 2.5 ns output fall time 7, 8 measured between 2.0v and 0.8v 2.5 ns output-to-output skew 7, 8 all outputs equally loaded 250 ps delay, clkin rising edge to clkout rising edge 8 measured at vdd /2 350 ps device-to-device skew 8 measured at vdd/2 on the clkout pins of the device 700 ps <8mhz 1.6 ns cycle-to-cycle jitter 7, 8 loaded outputs >8mhz 200 ps pll lock time 8 stable power supply, valid clock presented on clkin pin 1.0 ms note: 7. all parameters specified with 30pf loaded outputs. 8. parameter is guaranteed by design and characterization. not 100% tested in production
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 7 of 15 notice: the information in this document is subject to change without notice. switching waveforms duty cycle timing all outputs rise/fall time output - output skew input - output propagation delay t 2 t 1 v dd /2 v dd / 2 v dd / 2 output t 3 output 0v t 4 3.3v 0.8v 2v 0.8v 2v t 5 output output v dd /2 v dd /2 t 6 output input v dd /2 v dd /2
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 8 of 15 notice: the information in this document is subject to change without notice. device - device skew input-output skew test circuit a typical example of timing-safe? waveform v dd gnd clkout load output 0.1uf +3.3v 0.1uf +3.3v v dd t skew - one clock cycle n=1 t skew + input timing-safe? output t skew represents input-output skew when spread spectrum is on for example, t skew = 0.125 for an input clock12mhz, translates in to (1/12mhz) * 0.125=10.41ns input clkout with ssoff input timing-safe? clkout t 7 clkout, device 1 v dd /2 v dd /2 clkout, device 2
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 9 of 15 notice: the information in this document is subject to change without notice. package information 8-lead (150-mil) soic package d e h d a1 a2 a l c b e dimensions inches millimeters symbol min max min max a1 0.004 0.010 0.10 0.25 a 0.053 0.069 1.35 1.75 a2 0.049 0.059 1.25 1.50 b 0.012 0.020 0.31 0.51 c 0.007 0.010 0.18 0.25 d 0.193 bsc 4.90 bsc e 0.154 bsc 3.91 bsc e 0.050 bsc 1.27 bsc h 0.236 bsc 6.00 bsc l 0.016 0.050 0.41 1.27 0 8 0 8
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 10 of 15 notice: the information in this document is subject to change without notice. e h a a1 a2 d b c l e 8-lead tssop (4.40-mm body) dimensions inches millimeters symbol min max min max a 0.043 1.10 a1 0.002 0.006 0.05 0.15 a2 0.033 0.037 0.85 0.95 b 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.114 0.122 2.90 3.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.252 bsc 6.40 bsc l 0.020 0.028 0.50 0.70 0 8 0 8
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 11 of 15 notice: the information in this document is subject to change without notice. 16-lead (150 mil) molded soic package e h a a1 a2 d e b l c h seating plane d 0.004 pi n 1 id 1 8 916 dimensions inches millimeters symbol min max min max a 0.053 0.069 1.35 1.75 a1 0.004 0.010 0.10 0.25 a2 0.049 0.059 1.25 1.50 b 0.013 0.022 0.33 0.53 c 0.008 0.012 0.19 0.27 d 0.386 0.394 9.80 10.01 e 0.150 0.157 3.80 4.00 e 0.050 bsc 1.27 bsc h 0.228 0.244 5.80 6.20 h 0.010 0.016 0.25 0.41 l 0.016 0.035 0.40 0.89 0 8 0 8
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 12 of 15 notice: the information in this document is subject to change without notice. 16-lead tssop (4.40-mm body) d e h d a a1 b e l c a2 pin 1 id 1 8 9 16 seating plane dimensions inches millimeters symbol min max min max a 0.043 1.20 a1 0.002 0.006 0.05 0.15 a2 0.031 0.041 0.80 1.05 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.193 0.201 4.90 5.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.252 bsc 6.40 bsc l 0.020 0.030 0.50 0.75 0 8 0 8
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 13 of 15 notice: the information in this document is subject to change without notice. ordering code ordering code marking package type temperature pcs3p622z0xyg-08-st 3p622z0xyg 8-pi n 150-mil soic-tube, green commercial pcs3i622z0xyg-08-st 3i622z0xyg 8-pin 150-mil soic-tube, green industrial pcs3p622z0xyg-08-sr 3p622z0xyg 8-pin 150-mil soic-tape & reel, green commercial pcs3i622z0xyg -08-sr 3i622z0xyg 8-pin 150-mil soic-tape & reel, green industrial pcs3p622z0xyg-08-tt 3p622z0xyg 8-pin 4.4-mm tssop - tube, green commercial pcs3i622z00xyg -08-tt 3i622z0xyg 8-pin 4.4-mm tssop - tube, green industrial pcs3p622z0xyg-08-tr 3p622z0xyg 8-pin 4.4-mm tssop - tape & reel, green commercial pcs3i622z0xyg -08-tr 3i622z0xyg 8-pin 4.4-mm tssop - tape & reel, green industrial pcs3p622z0xyg -16-st 3p622z0xyg 16-pin 150-mil soic-tube, green commercial pcs3i622z0xyg -16-st 3i622z0xyg 16-pi n 150-mil soic-tube, green industrial pcs3p622z0xyg -16-sr 3p622z0xyg 16-pin 150-mil soic-tape & reel, green commercial pcs3i622z0xyg -16-sr 3i622z0xyg 16-pin 150-mil soic-tape & reel, green industrial pcs3p622z0xyg -16-tt 3p622z0xyg 16-pi n 4.4-mm tssop - tube, green commercial pcs3i622z0xyg -16-tt 3i622z0xyg 16-pin 4.4-mm tssop - tube, green industrial pcs3p622z0xyg -16-tr 3p622z0xyg 16-pin 4.4-mm tssop - tape & reel, green commercial pcs3i622z0xyg -16-tr 3i622z0xyg 16-pin 4.4-mm tssop - tape & reel, green industrial note: x=5 / 9; y=b / c
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 14 of 15 notice: the information in this document is subject to change without notice. device ordering information pcs3p622z0xyg-08-tr licensed under us patent #5,488,627, # 6,646,463 and #5,631,920. o = tsot23 u = msop j=tsot26 s = soic e = tqfp c=tdfn (2x2) col t = tssop l = lqfp a = ssop u = msop v = tvsop p = pdip b = bga d = qsop q = qfn x = sc - 70 device pin count x= automotive i= industrial p or n/c = commercial (-40c to +125c) (-40c to +85c) (0c to +70c) 1 = clock generator 6 = power management 2 = non pll based 7 = power management 3 = emi reduction 8 = power management 4 = ddr support products 9 = hi performance 5 = std zero dela y buffe r 0 = reserved pulsecore semiconductor mixed signal product part number f = lead free and rohs compliant part g = green package, lead free, and rohs r = tape & reel, t = tube or tray
PCS3P622Z05B/c may 2008 pcs3p622z09b/c rev 0.1 low frequency timing-safe? peak emi reduction ic 15 of 15 notice: the information in this document is subject to change without notice. ? copyright 2006 pulsecore semiconductor co rporation. all rights reserved. our logo and name are trademarks or registered trade marks of pulsecore semiconductor. all other brand and product names may be the trademarks of their respecti ve companies. pulsecore reser ves the right to make changes to this document and its products at any time without notice. pulsecore assumes no responsibility for any errors that may appear in this document. the data contained herein represents pu lsecore?s best data and/or estimates at the time of issuanc e. pulsecore reserves the right to change or correct this data at any time, without notice. if the product described herein is und er development, significant changes to these s pecifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. pulsecore does not assume any re sponsibility or liability arising out of t he application or use of any product descri bed herein, and disclaims any express or implied warranties related to the sale and/or use of pulsecore produc ts including liability or warrant ies related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agree d to in pulsecore?s terms and conditions of sale (which are available from pulsecor e). all sales of pulsecore products are made exclusively accordi ng to pulsecore?s terms and conditions of sale. the purchase of produc ts from pulsecore does not convey a license under any patent ri ghts, copyrights; mask works rights, trademarks, or any other intellectual property rights of pulsecore or third parties. pulsecore d oes not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of pulsecore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify pu lsecore against all claims arising from such use. pulsecore semiconductor corporation 1715 s. bascom ave suite 200 campbell, ca 95008 tel: 408-879-9077 fax: 408-879-9018 www. p ulsecoresemi.com copyright ? pulsecore semiconductor all rights reserved part number: PCS3P622Z05B/c pcs3p622z09b/c document version: 0.1 note: this product utilizes us patent # 6,646,463 impedance emulator patent issued to pulsecore semiconductor, dated 11-11-2003 many pulsecore semiconductor products are pr otected by issued patents or by applications for patent

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